As demands for sophisticated system clocks grow, phase-locked loops (PLLs) gradually prevail as a crucial component for generating multiple clocks. Referring to FIG. 1, a PLL 110 generally comprises a phase detector 112, a low-pass filter 114, an amplifier 116 and a voltage-controlled oscillator (VCO) 118. The phase detector 112 receives an input signal Vi and an output signal Vo from the VCO 118, and outputs a pulse signal Vd corresponding to a phase difference between the input signal Vi and the output signal Vo. The pulse signal Vd passes through the low-pass filter 114 to remove its high frequency components and to keep its low frequency components, and is then amplified by the amplifier 116 to control the VCO 118, such that a frequency of the output signal Vo steadily approaches a frequency of the input signal Vi. When the phase difference between the two signals stays constant, the frequency of the output signal Vo from the VCO 118 equals to that of the input signal Vi.
During the frequency-locking process, instead of staying constant, a bandwidth of the low-pass filter 114 gradually reduces as being controlled by a phase lock indicator 120. The phase lock indicator 120 first estimates the phase difference between the input signal Vi and the output signal Vo, and averages a plurality of estimated phase differences after a period of time to obtain an averaged phase difference value. According to the average value, the phase lock indicator 120 determines whether the PLL 110 is locked to the frequency of the input signal Vi. When it is determined that the PLL 110 is locked to the frequency of the input value Vi, the phase lock indicator 120 controls the low-pass filter 114 to reduce the bandwidth in order to maintain a current locked status. Under such circumstances, the PLL 110 is facilitated to more accurately lock to the frequency.
The phase lock indicator 120 simply calculates the average value of a plurality of phase differences to serve as basis for whether to change the bandwidth of the low-pass filter. However, the simple mechanism of calculating the average value is not adapted for all communication systems. To take cross-quadrature amplitude modulation (QAM) for example, it is known to those skilled in the related art that, as closer as a modulated signal gets to the center of the constellation, the smaller a signal-to-noise ratio the modulated signal has, and is more likely to be interfered with noise. It is to be noted that the cross-QAM is not applied to modulated signals located at corners of the constellation (shown as dotted points) but only to modulated signals located within the cross (shown as solid points). As a result, the input signal of the PLL 110 is highly prone to severe noise interference to lead to critical errors in the average value calculated by the phase lock indicator 120. Therefore, an overall performance of the PLL 110 gets rather unsatisfactory due to inaccurate determination of the PLL 110 based on the erroneous average value.